In conventional integrated circuit (IC) ESD protection schemes, special clamp circuits are often used to shunt ESD current between the IC power supply rails and thereby protect sensitive internal elements from damage. A type of ESD clamp circuit, known as an active metal oxide semiconductor field effect transistor (MOSFET) clamp circuit, typically consists of three functional elements; a trigger circuit, a buffer stage, and a large MOSFET transistor. The trigger circuit is designed to respond to an applied ESD event but remains inactive during normal operation of the IC. The buffer stage is used to invert and amplify the trigger output in order to drive the gate terminal of the large MOSFET transistor. The large MOSFET transistor, connected between the two power supply rails, acts as the primary ESD current dissipation device in the clamp circuit. Active MOSFET clamp circuits typically rely on only MOSFET action to absorb ESD events, and since the peak current in an ESD event is on the order of amperes, large MOSFET transistor sizes are required.
A known RC-triggered active MOSFET ESD clamp circuit 50 is shown in FIG. 1. The clamp circuit 50 in FIG. 1 protects a V.sub.DD power supply rail 5 from positive ESD events referenced to a grounded V.sub.SS power supply rail 10. As shown in FIG. 1, clamp circuit 50 employs a trigger circuit 15, a buffer stage 20, and a large N-channel MOSFET (NMOSFET) transistor 25. Trigger circuit 15 is designed as a resistor-capacitor (RC) transient detector, utilizing resistor 30 and capacitor 35. In response to an ESD event that induces a rapid positive voltage transient on the V.sub.DD rail 5, trigger circuit 15 initially holds a node 40 well below V.sub.DD. The inverter stage 20, with an input connected to node 40, then drives the gate of NMOSFET 25 to V.sub.DD. Once turned on, NMOSFET transistor 25 provides a low resistance shunt between the V.sub.DD rail 5 and the VSS rail 10. NMOSFET 25 will remain conductive for a period of time which is determined by the RC time constant of trigger circuit 15. As a result, it is critical that this RC time constant is long enough to exceed the maximum expected duration of an ESD event, typically a few hundred nanoseconds, while short enough to avoid false triggering of the clamp circuit during normal ramp-up of the V.sub.DD power rail, typically a few milliseconds. During normal operation of the IC, with a constant V.sub.DD power supply level, NMOSFET 25 is biased in a nonconductive state.
A limitation with the clamp circuit of prior art FIG. 1 is that such a clamp circuit encompasses a large substrate area. The large size of NMOSFET 25 is unavoidable since the performance of an active MOSFET ESD clamp circuit is directly proportional to the channel width (dimension perpendicular to current flow) of this primary current dissipation device. The NMOSFET 25 channel length (dimension parallel to current flow) is typically set to the semiconductor process design rule minimum so as to achieve the minimum on-state resistance in the device. However, other portions of the clamp circuit, particularly the trigger circuit 15, occupy a significant portion of the overall clamp area. The area utilized by trigger circuit 15, including resistor 30 and capacitor 35, commonly represents twenty to fifty percent of the area required for NMOSFET transistor 25. Trigger circuit 15 requires this significant area in order to achieve the required RC time constant of a few hundred nanoseconds. Capacitor 35 is typically formed from a NMOSFET transistor with its source, drain, and body connected to V.sub.SS, and its gate connected to node 40. Resistor 30 is typically formed from a PMOSFET transistor with its source and body connected to V.sub.DD, its drain connected to node 40, and its gate connected to V.sub.SS. PMOSFET resistor 30 is typically sized with a minimum channel width and maximum channel length so as to achieve the maximum possible device resistance. The limits for these dimensions are set by semiconductor process design rules in order to insure manufacturability and consistency in electrical characteristics. Therefore, in a given semiconductor process, there is a limit to the maximum resistance which may be achieved with PMOSFET resistor 30. NMOSFET capacitor 35 must then be sized to produce the required RC time constant, with the typical result that this capacitor dominates the area utilized by trigger circuit 15. A reduction in the size of trigger circuit 15, particularly a reduction in the size of the NMOSFET capacitor 35, would provide a more space efficient ESD clamp circuit.
Another limitation with the RC triggered clamp circuit of prior art FIG. 1 is susceptibility to false triggering during normal ramp-up of the V.sub.DD power supply. These clamp circuits are at risk in IC applications where the V.sub.DD power supply ramp-up time is on the order of the trigger circuit 15 RC time constant. ICs in battery powered applications may see a rapid rise in V.sub.DD as the battery is connected. In addition, certain applications require ICs be inserted into powered up systems. This "hot-plugging" often results in a very rapid ramp-up of the IC V.sub.DD power supply rail. Accordingly, there is a need for a clamp circuit which is more tolerant of a rapid ramp-up of the V.sub.DD power supply.
In addition to the need to reduce the size and improve the performance of ESD clamp circuits, there is a further need to form more efficient rail clamp circuits that are capable of providing ESD protection for ICs having multiple power supply potentials. Many IC designs allow voltages in excess of the internal power supply voltage specified for a baseline process technology to be brought on board the chip. Protecting this higher voltage power rail can be achieved with stacked, or series-connected active MOSFET ESD clamp circuits. One such prior art circuit which utilizes stacked active MOSFET rail clamps is described in U.S. Pat. No. 5,654,862, assigned to Rockwell International Corporation and summarized in prior art FIG. 2. This prior art circuit, shown schematically in FIG. 2 utilizes a stacked active MOSFET clamp circuit to protect multiple power rails. In FIG. 2, three power supply rails are shown and labeled V.sub.DDH 55, V.sub.DDL 60, and V.sub.SS 65. A first NMOSFET 70 and a second NMOSFET 75 are serially connected between an ESD Bus 80 and the V.sub.SS power supply rail 65. The gate electrode of both NMOSFET 70 and NMOSFET 75 is controlled by an ESD trigger and bias circuit 85. A diode 90 has an anode connected to supply voltage V.sub.DDH 55 and a cathode connected to ESD bus 80. A diode 95 has an anode connected to supply voltage V.sub.DDL and a cathode connected to ESD Bus 70. During an ESD event coupled through either V.sub.DDH or V.sub.DDL referenced to V.sub.SS, diode 90 or diode 95 will forward bias, raising the potential of ESD Bus 80. ESD trigger and bias circuit 85 senses the transient and biases clamp transistors 70 and 75 into a conductive state to dissipate current from ESD Bus 80 to V.sub.SS 65.
It is assumed that V.sub.DDL represents the semiconductor process maximum specified power supply voltage for NMOSFETs 70 and 75. This assumption implies that no voltage in excess of V.sub.DDL may be applied across the gate oxide of either NMOSFET in normal operation. The NMOSFETs 70 and 75 are stacked in order that the clamp circuit may protect a power supply rail with voltage greater than V.sub.DDL by stepping this voltage across two gate oxides. With proper bias conditions on these stacked NMOSFETs, V.sub.DDH may operate at twice V.sub.DDL without exceeding the gate oxide voltage limit on either NMOSFET 70 or 75. Under normal IC operation, the ESD Bus 80 will eventually charge up to the potential of V.sub.DDH 55. With the ESD Bus voltage as high as twice V.sub.DDL, the series combination of NMOSFETs 70 and 75 must remain nonconductive with no more than V.sub.DDL applied across either NMOSFET gate oxide. To achieve this, the ESD trigger and bias circuit 85 must bias the gate of NMOSFET 70 to a voltage intermediate between V.sub.DDH and V.sub.DDL, and bias the gate of NMOSFET 75 to V.sub.SS.
An issue with the stacked clamp circuit of prior art FIG. 2 is the significant increase in area required to produce ESD performance comparable to the single clamp circuit shown in prior art FIG. 1. For identically sized devices, the series combination of NMOSFETs 70 and 75 in FIG. 2 obviously produce a higher resistance clamp circuit than the single NMOSFET 25 in FIG. 1. To achieve ESD performance comparable to the single NMOSFET clamp circuit in FIG. 1, the series NMOSFETs 70 and 75 must each be sized with a channel width about twice the width of NMOSFET 25. Therefore, alternate configurations of the stacked clamp circuit, which would allow for smaller sizes of NMOSFETs 70 and 75, yet provide comparable ESD protection, would be desirable.
A limitation with the stacked clamp circuit of prior art FIG. 2 is that the series NMOSFETs 70 and 75 must be sized to protect the most ESD sensitive elements on the IC, whether they are served by the V.sub.DDL or V.sub.DDH power supply rails. However, in many ICs with multiple power supply voltages, the elements which are served by the V.sub.DDL power supply rail are more sensitive to ESD damage than elements served by the V.sub.DDH power supply rail. In the clamp circuit of prior art FIG. 2, stacked NMOSFETs 70 and 75 are sized to protect V.sub.DDL for positive ESD events referenced to V.sub.SS even though a less resistive single NMOSFET could be used as the primary ESD current dissipation device for ESD events coupled through this lower voltage power supply. Elements on the IC which are served by the V.sub.DDH power rail, and assumed less susceptible to ESD damage, could be adequately protected by stacked NMOSFETs of smaller channel width. Accordingly, a need exists for a stacked active MOSFET ESD clamp circuit which retains the advantages of series NMOSFETs to protect a higher voltage power rail, while providing a single NMOSFET as the primary ESD current dissipation device for protecting a lower voltage power rail.
Yet another limitation with the clamp circuit taught by U.S. Pat. No. 5,654,862 is associated with the biasing of the clamp transistors themselves as can be readily seen from FIG. 5 therein. Although an ESD trigger and bias circuit (transistors 552, 560, 561 and resistor 550 of FIG. 5 in U.S. Pat. No. 5,654,862) makes each of two clamp transistors (501, 502) conductive at the same time, the two clamp transistors are not made equally conductive due to differing gate-to-body voltage potentials. During an ESD event, transistor 501 has the full voltage difference between V.sub.ESD and V.sub.SS applied across its gate and body terminals, whereas transistor 502 has a smaller voltage difference applied across its gate and body terminals. As a result, during an ESD event, one clamp transistor is significantly more conductive than the other series-connected clamp transistor, resulting in significantly increased overall clamp resistance. Accordingly, a need exists for an improved bias network for a stacked active MOSFET ESD clamp circuit.
Thus, a need exists for improved ESD protection that alleviates the problems in the prior art as described above.